The present invention relates to a semiconductor device for memories, logic circuits and the like which require a high integrability and a method of producing the same.
A report of analysis about a gate overlapped drain (LDD) structure as shown in FIG. 1 for improving a characteristic of an SOISMOSFET by Yamaguchi et al is disclosed in the "1990 IEDM Technical Digest".
In FIG. 1, the reference numeral 101 depicts a silicon substrate, 102 a silicon dioxide film, 103 a low impurity concentration p-type region, 104 a low impurity concentration n-type region, 105 a high impurity concentration n-type region, 106 a gate dioxide film and 107 a gate electrode.
As a structure of the SOISMOSFET for suppressing a drain voltage induced barrier height reduction effect, a structure of an XMOS transistor with a top gate and a bottom gate as shown in FIG. 2 is reported by T. Sekigawa et al in the "Solid State Electronics", of 1984, Vol.27, p.827 and further a structure of the SOISMOSFET with a potential fixed back gate as shown in FIG. 3 is reported by M. Fukuma in the "1988 Symposium on VLSI Technology Digest of Technical Papers" p.7.
In FIG.2, the numeral 108 depicts a silicon substrate, 109 a silicon dioxide film, 110 a silicon dioxide film, 111 an upper gate electrode, 112 a lower gate electrode, 113 a channel region, 114 a source and 115 a drain after "a drain". The number 16 indicates a gate oxide film.
In FIG. 3, 117 depicts a high impurity concentration p-type silicon substrate, 118 and 122 silicon dioxide films, 119, 121 a high impurity concentration n-type region, 120 a neutral silicon region and 123 a gate electrode. The number 122 indicates an insulating film for insulating the gate electrode 123.
Still further, a method of exercising an electric field relaxation of the MOSFET produced on the bulk wafer at the source and drain regions in the vertical structure as shown in FIG. 4 was proposed by A. L. F. Tasch. et al and is disclosed in the "1990 Symposium on VLSI Technology Digest of Technical Papers", p.43.
In FIG. 4, the numeral 124 depicts a silicon substrate, 125 a high impurity concentration n-type region, 126 a low impurity concentration n-type region, 127 a second high impurity concentration n-type region, 128 a silicon dioxide film and 129 a gate electrode.
There are two problems in realization of the short channel of the SOISMOSFET. The first one is a floating substrate effect which is likely caused by an impact ionization with an increase of a lateral electric field intensity at the drain end as reported by Yoshimi et al in the "IEEE Transaction of Electron Devices" ED37 No.9, in 1990, p.2015.
The second one is a short channel effect with a punchthrough which are caused by the barrier height reduction owing to an electric field from the drain.
To solve the foregoing problems, the conventional measure as shown in FIG. 1 provides low impurity concentration regions at the source and the drain regions entailing, however, an increase of a region of the transistor in proportion to the low impurity concentration area to prevent a high integration.
While, in the conventional bulk MOSFET as shown in FIG. 2, the vertical deposit structure brings a field relaxation to suppress an increase of an area of the low impurity concentration region but there occurs the problems of parasitic capacities of gate side wall to source and/or drain as well as an electric field concentration at the corner under the gate electrode.
The conventional MOSFETs as shown in FIGS. 3 and 4 are considered as suitable structures to overcome the second problem, while a combination with another measure is required to overcome the first problem.